DocumentCode
1125555
Title
An ECO routing algorithm for eliminating coupling-capacitance violations
Author
Xiang, Hua ; Chao, Kai-Yuan ; Wong, Martin D F
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY
Volume
25
Issue
9
fYear
2006
Firstpage
1754
Lastpage
1762
Abstract
Engineering change order changes are almost inevitable in the late stages of a design process. Based on an existing design, incremental change is favored since it can avoid considerable efforts of redoing the whole process and can minimize the disturbance on the existing converged design. The coupling-capacitance violation elimination (CVE) problem is addressed. Due to the changes in the multiple layer routing design, the total coupling capacitance on some signal wire segments on a layer may be larger than their allowable bounds after postlayout timing/noise analysis. The target is to find a new routing solution without coupling-capacitance violations under certain constraints, which helps to keep the new design close to the original one. This paper proposes a two-stage algorithm to solve CVE problems, and present optimization strategies to speed up the execution. Experimental results demonstrate the efficiency and effectiveness of this algorithm
Keywords
capacitance; circuit layout CAD; integrated circuit layout; integrated circuit noise; network routing; CVE problem; ECO routing algorithm; coupling-capacitance violation elimination; design process; engineering change order; multiple layer routing design; noise analysis; optimization strategies; postlayout timing; signal wire segments; Algorithm design and analysis; Capacitance; Chaos; Crosstalk; Helium; Rails; Routing; Semiconductor device noise; Signal design; Wires; Coupling capacitance; engineering change order (ECO); routing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.857396
Filename
1673749
Link To Document