DocumentCode
1125644
Title
An algorithmic technique for diagnosis of faulty scan chains
Author
Guo, Ruifeng ; Venkataraman, Srikanth
Author_Institution
Intel Corp., Hillsboro, OR
Volume
25
Issue
9
fYear
2006
Firstpage
1861
Lastpage
1868
Abstract
This paper presents an algorithmic scan-chain-fault diagnosis procedure. The diagnosis for a single scan-chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to identify the suspect scan cell within a range of scan cells. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold-time faults). The application of the procedure in a production test flow is discussed. Simulation and silicon results from several products show the effectiveness of the proposed method
Keywords
automatic test pattern generation; boundary scan testing; design for testability; elemental semiconductors; fault simulation; silicon; chain test patterns; diagnostic resolution; fault type; faulty chain; hold-time faults; production test flow; scan chain fault diagnosis; stuck-at faults; suspect scan cell; timing failures; transition faults; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Design for testability; Fault diagnosis; Logic; Production; Silicon; Timing; Defect; diagnosis; fault isolation; fault simulation; scan chain;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.858267
Filename
1673757
Link To Document