Title :
Analytical bound for unwanted clock skew due to wire width variation
Author :
Rajaram, Anand ; Lu, Bing ; Hu, Jiang ; Mahapatra, Rabi ; Guo, Wei
Author_Institution :
Texas Instrum. Inc., Dallas, TX
Abstract :
Under modern very large-scale integrated technology, process variations greatly affect circuit performance, especially clock skew, which is very timing sensitive. Unwanted skew due to process variation forms a bottleneck, preventing further improvement on clock frequency. Impact from intrachip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature. Through wire shaping analysis, the authors establish an analytical bound for the unwanted skew due to wire width variation, which is a nonnegligible factor among interconnect variations. Experimental results on benchmark circuits show that this bound is safer, tighter, and computationally faster than similar existing approach
Keywords :
VLSI; clocks; integrated circuit design; analytical bound; benchmark circuits; circuit performance; clock frequency; process variation; unwanted clock skew; very large scale integrated; wire shaping analysis; wire width variation; Circuit optimization; Clocks; Feedback; Frequency; Integrated circuit interconnections; Integrated circuit technology; Performance analysis; Timing; Very large scale integration; Wire; Clock skew; VLSI; variation;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.857398