Title :
Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process
Author :
Ortolland, Claude ; Okuno, Yasutoshi ; Verheyen, Peter ; Kerner, Christoph ; Stapelmann, Chris ; Aoulaiche, Marc ; Horiguchi, Naoto ; Hoffmann, Thomas
Author_Institution :
Interuniversity Microelectron. Center, Leuven, Belgium
Abstract :
In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.
Keywords :
CMOS integrated circuits; logic gates; semiconductor device models; stress analysis; CMOS technology; NMOS device; PMOS device; fully silicided polysilicon gates; maskless SMT integration; metal inserted polysilicon gates; nonselective process; stress memorization technique; Annealing; CMOS process; CMOS technology; Capacitive sensors; Degradation; Helium; MOS devices; Silicon; Stress; Surface-mount technology; Fully silicided (FUSI) polysilicon gate; metal gate [metal inserted polysilicon (MIPS)]; strained silicon; stress memorization technique (SMT);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2009.2024021
