Towards Power Optimization and Implementation of Probabilistic Circuits Using Single-Electron Technology

With continuous CMOS technology scaling toward its physical limits, there has been a growing demand for next-generation technologies with nanometer scale and novel design architectures. Single-electron (SE) technology is one of those candidates that can lead to high density and low power consumption for large-scale integration, at a cost of reduced reliability. Considering the fact that probabilistic circuits are able to realize fault-tolerant architectures, implementing probabilistic circuits with SE technology would be a natural solution for future electronic applications. In this paper, we first study the probabilistic behavior and implementation of SE logic, and show an exponential relation between logic gate´s reliability and its energy consumption. A gate-level power optimization for probabilistic circuits is then proposed to minimize their power cost under given reliability constraints. Comparison with simulated annealing (SA) based method shows that the proposed approach can obtain promising results within a reasonably short time.