Title :
Hierarchical Verification of Galois Field Circuits
Author :
Mukhopadhyay, Debdeep ; Sengar, Gaurav ; Chowdhury, Dipanwita Roy
Author_Institution :
Indian Inst. of Technol., Madras
Abstract :
This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.
Keywords :
Galois fields; formal verification; logic design; multiplying circuits; Galois field architecture circuits; composite field; formal hardware verification; hierarchical verification; multipliers; reduced ordered functional decision diagram; Arithmetic; Boolean functions; Circuits; Computer science; Cryptography; Data structures; Digital signal processing; Formal verification; Galois fields; Hardware; Composite field; Galois fields; formal verification; functional decision diagrams (DDs); hierarchical; multipliers;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2007.895755
