• DocumentCode
    112664
  • Title

    Analysis of Effective Gate Length Modulation by X-Ray Irradiation for Fully Depleted SOI p-MOSFETs

  • Author

    Kurachi, Ikuo ; Kobayashi, Kazuo ; Okihara, Masao ; Kasai, Hiroki ; Hatsui, Takaki ; Hara, Kazuhiko ; Miyoshi, Toshinobu ; Arai, Yasuo

  • Author_Institution
    High Energy Accel. Res. Organ., Tsukuba, Japan
  • Volume
    62
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    2371
  • Lastpage
    2376
  • Abstract
    An X-ray irradiation degradation mechanism has been investigated for fully depleted-silicon-on-insulator (FD-SOI) p-channel MOSFETs (p-MOSFETs). It is found that the drain current degradation by the X-ray irradiation has gate length dependence showing 20% degradation for L = 0.2 μm, while 8% for L = 10 μm after the 1.4 kGy(Si) X-ray irradiation. Using Terada´s method, it was found that the degradation is not due to mobility degradation but due to radiation-induced gate length modulation (RIGLEM) and the associated increase of source and drain parasitic resistance. The major cause of degradation induced by the RIGLEM is explained by an analytical model, assuming a positive charge generation in sidewall spacers. It can be suggested that the X-ray irradiation degradation of FD-SOI p-MOSFET can be improved by optimizing the lightly doped drain region.
  • Keywords
    MOSFET; elemental semiconductors; radiation hardening (electronics); silicon; silicon-on-insulator; RIGLEM; Si; Teradas method; X-ray irradiation degradation mechanism; drain current degradation; drain parasitic resistance; effective gate length modulation; fully depleted SOI p-MOSFETs; p-channel MOSFET; positive charge generation; radiation absorbed dose 1.4 kGy; radiation-induced gate length modulation; sidewall spacers; silicon-on-insulator; source parasitic resistance; Degradation; Logic gates; MOSFET; MOSFET circuits; Modulation; Radiation effects; Resistance; Fully depleted-silicon-on-insulator (FD-SOI); MOSFET; X-ray radiation hardness; X-ray radiation hardness.; gate length modulation; sidewall spacer;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2015.2443797
  • Filename
    7138596