DocumentCode
1127561
Title
A simplified low-voltage smart power technology
Author
Berta, F. ; Fernandez, J. ; Hidalgo, S. ; Godignon, P. ; Rebollo, J. ; Millan, J.
Author_Institution
Centro Nacional de Microelectronica, Barcelona, Spain
Volume
12
Issue
9
fYear
1991
Firstpage
465
Lastpage
467
Abstract
A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate.<>
Keywords
MOS integrated circuits; integrated circuit technology; power integrated circuits; MOS transistors; Zeners; diodes; high-value isolated capacitors; high-voltage PMOS; lateral n-p-n bipolar transistors; low mask count; low-voltage CMOS; polysilicon-gate VDMOS process; self-isolated low-voltage smart power technology; vertical n-p-n bipolar transistors; Bipolar transistors; CMOS logic circuits; CMOS technology; Circuit simulation; Diodes; Implants; Logic devices; MOS capacitors; MOSFETs; Oxidation;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.116919
Filename
116919
Link To Document