Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness

The effect of the Si-SiO/sub 2/ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH/sub 4/OH in the NH/sub 4/OH-H/sub 2/O/sub 2/-H/sub 2/O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO/sub 2/ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm/sup 2//V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5*10/sup 17/ cm/sup -3/, i.e. the electron bulk mobility is 400 cm/sup 2//V-s. It goes down to 100 cm/sup 2//V-s when the interface microroughness exceeds 1 nm.<>