VLSI implementation of a neural network model

Author

Graf, Hans P. ; Jackel, Lawrence D. ; Hubbard, Wayne E.

Author_Institution

AT&T Bell Lab., Holmdel, NJ, USA

Volume

21

Issue

3

fYear

1988

fDate

3/1/1988 12:00:00 AM

Firstpage

41

Lastpage

49

Abstract

The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip´s behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network.<>

Keywords

CMOS integrated circuits; VLSI; computerised pattern recognition; neural nets; CMOS; VLSI; associative memory; complementary metal-oxide-semiconductor; coprocessor; neural network model; parallel processing; pattern classifier; pattern-recognition; programmable connection matrix; Biological system modeling; Circuit testing; Computer networks; Integrated circuit interconnections; Neural networks; Optical computing; Optical fiber networks; Optical interconnections; Optical network units; Very large scale integration;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.30

Filename

30