Technology limitations for N/sup +//P/sup +/ polycide gate CMOS due to lateral dopant diffusion in silicide/polysilicon layers

Author

Chu, Charles L. ; Chin, Goodwin ; Saraswat, Krishna C. ; Wong, S. Simon ; Dutton, Robert

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

12

Issue

12

fYear

1991

Firstpage

696

Lastpage

698

Abstract

The device degradation of dual-polycide-gate N/sup +//P/sup +/ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher-temperature furnace steps. Simulations show that CoSi/sub 2/ and TiSi/sub 2/ appear to be better candidates for submicrometer dual-gate applications than WSi/sub 2/.<>

Keywords

CMOS integrated circuits; VLSI; cobalt compounds; integrated circuit technology; metallisation; titanium compounds; CMOS polycide transistors; CoSi/sub 2/; TiSi/sub 2/; coupled 2-D process; design rule spacings; device degradation; device simulator; dual-polycide-gate; gate area ratios; lateral diffusion of dopants; lateral dopant diffusion; low temperature processing; micron spacings; polycide gate CMOS; scaling; short higher-temperature furnace steps; silicide technologies; silicide/polysilicon layers; silicides; simulations; submicrometer dual-gate; submicrometer spacings; technology limitations; thermal processing conditions; Annealing; CMOS process; CMOS technology; Furnaces; MOS devices; MOSFETs; Reservoirs; Silicides; Silicon; Thermal degradation;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.116959

Filename

116959