Title :
Size limits on phased burst error correcting array codes
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Abstract :
A method for finding allowed array sizes for two-dimensional phased burst error correcting array codes is presented. These arrays codes have simple parity checks on two axes, have diagonal read-out, and are capable of correcting phased bursts along any one diagonal.
Keywords :
error correction codes; magnetic storage; 2D array codes; ECC; array sizes; computer memories; diagonal read-out; error correcting array codes; magnetic storage; parity checks; phased burst error; size limits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19900036
