DocumentCode
1128508
Title
Topology adaptive network-on-chip design and implementation
Author
Bartic, T.A. ; Mignolet, J.-Y. ; Nollet, V. ; Marescaux, T. ; Verkest, D. ; Vernalde, S. ; Lauwereins, R.
Author_Institution
IMEC, Leuven, Belgium
Volume
152
Issue
4
fYear
2005
fDate
7/8/2005 12:00:00 AM
Firstpage
467
Lastpage
472
Abstract
Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput.
Keywords
hardware description languages; logic CAD; reconfigurable architectures; system-on-chip; billion-transistor system-on-chip development; flexible network design; irregular topologies; reconfigurable systems; topology adaptive network-on-chip design;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:20045016
Filename
1492059
Link To Document