An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation

Author

Boeuf, Frédéric ; Sellier, Manuel ; Farcy, Alexis ; Skotnicki, Thomas

Author_Institution

STMicroelectronics, Crolles

Volume

55

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

1433

Lastpage

1440

Abstract

In this paper, using the new generation of model for assessment of CMOS technologies and roadmaps software, we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation, and variability, such as loaded ring-oscillator delay, as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%-per-year delay improvement to construct a new industrially viable roadmap.

Keywords

CMOS logic circuits; SRAM chips; integrated circuit interconnections; 6T-SRAM functionality; CMOS interconnects; CMOS technology roadmap; loaded ring-oscillator delay; power dissipation; CMOS logic circuits; CMOS technology; Circuit optimization; Delay; Fluctuations; Integrated circuit interconnections; Power dissipation; SPICE; Semiconductor device modeling; Semiconductor process modeling; CMOS integrated circuits; CMOS roadmaps; MOSFET logic devices; SRAM chips; logic design; semiconductor logic devices; variability;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2008.921274

Filename

4488218