Title :
Modeling and analysis of parametric yield under power and performance constraints
Author :
Rao, Rajeev R. ; Blaauw, David ; Sylvester, Dennis ; Devgan, Anirudh
Author_Institution :
Michigan Univ., Ann Arbor, MI, USA
Abstract :
Leakage current is a stringent constraint in today´s ASIC designs. Effective parametric yield prediction must consider leakage current´s dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.
Keywords :
application specific integrated circuits; integrated circuit design; integrated circuit yield; leakage currents; logic gates; logic testing; ASIC design; application specific integrated circuit; chip frequency; logic gates; parametric yield prediction; subthreshold leakage current; Circuits; Design automation; Equations; Frequency estimation; IEEE Press; Leakage current; Low power electronics; Performance analysis; Subthreshold current; Yield estimation; B.7 Integrated Circuits; Fault-Tolerance; G.4.g Reliability and robustness;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2005.89
