DocumentCode :
1129109
Title :
An all-digital DFT scheme for testing catastrophic faults in PLLs
Author :
Azaïs, Florence ; Bertrand, Yves ; Renovell, Michel ; Ivanov, André ; Tabatabaei, Sassan
Author_Institution :
LIRMM, Univ. of Montpellier, France
Volume :
20
Issue :
1
fYear :
2003
Firstpage :
60
Lastpage :
67
Abstract :
Traditional functional testing of mixed-signal ICs is slow and requires costly, dedicated test equipment. The authors update the standard PLL architecture to allow simple digital testing. The all-digital strategy yields catastrophic fault coverage as high as that of the classical functional test, plus it is fast, extremely simple to implement, and requires only standard digital test equipment.
Keywords :
design for testability; fault simulation; integrated circuit testing; mixed analogue-digital integrated circuits; phase locked loops; PLL architecture; all-digital DFT scheme; catastrophic fault testing; digital test equipment; digital testing; functional testing; mixed-signal ICs; Circuit testing; Delay; Low pass filters; Multivalued logic; Phase frequency detector; Phase locked loops; Test equipment; Time measurement; Voltage control; Voltage-controlled oscillators;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2003.1173054
Filename :
1173054
Link To Document :
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