Low-power low-area network-on-chip architecture using adaptive electronic link buffers

In the deep sub-micron regime, the performance of network-on-chip (NoC) architectures is bound by the limited power and area budget. Proposed is a low-power low-area NoC architecture using a novel power-efficient control circuit that enables repeaters along the inter-router links to function as adaptive link buffers, thereby reducing the number of buffers required in the router. Simulation results in the 90 nm technology show power savings of nearly 45% and area savings of 50% for the proposed technique.