Title :
An efficient prime-factor algorithm for the discrete cosine transform and its hardware implementations
Author :
Lee, Peizong ; Huang, Fang-Yu
Author_Institution :
Inst. of Inf. Sci., Acad. Sinica, Taipei, Taiwan
fDate :
8/1/1994 12:00:00 AM
Abstract :
The prime-factor decomposition is a fast computational technique for many important digital signal processing operations, such as the convolution, the discrete Fourier transform, the discrete Hartley transform, and the discrete cosine transform (DCT). The authors present a new prime-factor algorithm for the DCT. They also design a prime-factor algorithm for the discrete sine transform based on the prime-factor DCT algorithm. Hardware implementations for the prime-factor DCT are also studied. They are especially interested in the hardware designs which are suitable for the VLSI implementations. They show three hardware designs for the prime-factor DCT, including a VLSI circuit fabricated directly according to the signal-flow graph, a linear systolic array, and a mesh-connected systolic array. These three designs show the trade-off between cost and performance. The methodology, which deals with general (N1× N2)-point DCTs, where N1 and N2 are mutually prime, is illustrated by converting a 15-point DCT problem into a (3×5)-point 2D DCT problem
Keywords :
VLSI; digital signal processing chips; discrete cosine transforms; signal processing; systolic arrays; VLSI implementation; computational technique; digital signal processing operations; discrete cosine transform; discrete sine transform; efficient prime-factor algorithm; hardware implementations; linear systolic array; mesh-connected systolic array; prime-factor decomposition; signal-flow graph; Algorithm design and analysis; Convolution; Digital signal processing; Discrete Fourier transforms; Discrete cosine transforms; Fast Fourier transforms; Hardware; Signal processing algorithms; Systolic arrays; Very large scale integration;
Journal_Title :
Signal Processing, IEEE Transactions on