Phase-Frequency Detection in Sampled Phase-Locked Frequency Mlultipliers

Phase-locked high-frequency multipliers which do not have powergreedy frequency dividers in the feedback loop, but which do have a sample-and-hold circuit as a phase detector are hard to design, due to conflicting requirements which determine the choice for loop gain and loop bandwidth. A circuit is described that acts as a frequency control if the loop is not locked and as a phase control once the loop can be locked. The loop filter has to be optimized for the locked condition only, and the allowable preset error is more than 80 percent of the sample frequency. The circuit also indicates whether the oscillator frequency is an odd or an even multiple of the sample frequency. Pull-in is at least an order of magnitude faster than with phase control alone.