Design for concurrent error detection and testability in storage/logic arrays

Author

Savin, Howard V. ; Bucknell, Mary S. ; Spaulding, Marc D. ; Maciukenas, Thomas B. ; Fuchs, W. Kent

Author_Institution

Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA

Volume

29

Issue

7

fYear

1994

fDate

7/1/1994 12:00:00 AM

Firstpage

770

Lastpage

779

Abstract

Storage/Logic Arrays (SLA´s) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and multiple levels of logic. A means of designing SLA´s for ease of testability and concurrent error detection (CED) is provided in this paper. Test sets for static and dynamic CMOS circuits are described. Fault and error coverage is presented and performance and area costs are analyzed for example circuits. In addition, a means of implementing dynamic CMOS SLA´s is presented and shown superior to previous NMOS, static CMOS, and dynamic CMOS approaches based upon power consumption and simplicity of design

Keywords

CMOS integrated circuits; VLSI; design for testability; error detection; integrated circuit testing; integrated logic circuits; logic arrays; logic design; logic testing; sequential circuits; VLSI sequential logic; concurrent error detection; dynamic CMOS circuits; error coverage; fault coverage; power consumption; static CMOS circuits; storage/logic arrays; structured logic array; testability; CMOS logic circuits; CMOS memory circuits; Circuit analysis; Circuit faults; Circuit testing; Costs; Logic arrays; Logic design; Logic testing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.303714

Filename

303714