High-speed low-power direct-coupled complementary push-pull ECL circuit

Author

Chuang, C.T. ; Chin, K.

Author_Institution

T.J. Watson Res. Centre, IBM Res. Div., Yorktown Heights, NY, USA

Volume

29

Issue

7

fYear

1994

fDate

7/1/1994 12:00:00 AM

Firstpage

836

Lastpage

839

Abstract

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-μm double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit

Keywords

VLSI; bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; 0.8 micron; VLSI; collector load resistor; direct tapping; direct-coupled complementary push-pull ECL circuit; direct-coupled npn pull-down scheme; direct-coupled pnp pull-up scheme; double-poly self-aligned complementary bipolar process; load driving capability; loaded delay; self-terminating dynamic current pulse; switching transient; voltage levels; Coupling circuits; Delay; Diodes; Helium; Power dissipation; Resistors; Switches; Switching circuits; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.303723

Filename

303723