Title :
On the Three-Valued Simulation of Digital Systems
Author_Institution :
Department of Computer Science, Queens College of the City University of New York
Abstract :
The problem of the so-called "pessimistic" results, obtained by usingg three-valued (0,1,u) simulation for design verification of digital systems, is discussed. A complete three-valued model for the sequential portion of the digital systems is suggested. The conventional gate model is replaced by the new model, which reduces the problem considerably.
Keywords :
Partial synchronization, sequential circuit, simulation, synchronizing sequence, three-valued.; Algebra; Circuit simulation; Digital systems; Flip-flops; Hazards; Master-slave; Sequential circuits; Steady-state; Transient analysis; Uncertainty; Partial synchronization, sequential circuit, simulation, synchronizing sequence, three-valued.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1976.1674571
