• DocumentCode
    1131942
  • Title

    On the Three-Valued Simulation of Digital Systems

  • Author

    Mor, Meir

  • Author_Institution
    Department of Computer Science, Queens College of the City University of New York
  • Issue
    11
  • fYear
    1976
  • Firstpage
    1152
  • Lastpage
    1156
  • Abstract
    The problem of the so-called "pessimistic" results, obtained by usingg three-valued (0,1,u) simulation for design verification of digital systems, is discussed. A complete three-valued model for the sequential portion of the digital systems is suggested. The conventional gate model is replaced by the new model, which reduces the problem considerably.
  • Keywords
    Partial synchronization, sequential circuit, simulation, synchronizing sequence, three-valued.; Algebra; Circuit simulation; Digital systems; Flip-flops; Hazards; Master-slave; Sequential circuits; Steady-state; Transient analysis; Uncertainty; Partial synchronization, sequential circuit, simulation, synchronizing sequence, three-valued.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1976.1674571
  • Filename
    1674571
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1131942