High throughput parallel montgomery modular exponentiation on FPGA

Modular exponentiation is the key operation in public key cryptosystems such as RSA (Rivest, Shamir Adelman). It is implemented by repeated modular multiplications which are time consuming for large operands. Accelerating RSA requires reducing the number of modular multiplications with speeding up the modular multiplication. In this paper, we present a high throughput architecture implementing a fast modular exponentiation based on the square-and-multiply method, called binary method which allows the parallel execution of squares and multiplications by using two fast Montgomery modular multipliers. The Montgomery multiplication is based on a high radix-2¹⁶ to reduce the iterations number of this operation where the multiplication of two 1024-bits numbers is performed in only 65 iterations. The CS (Carry Save) representation is advantageously used to overcome the carry propagation then the iteration cycle is independent of the data path length. The implementation results showed that the architecture computes a 1024 bits modular exponentiation in only 0.66 ms.