Analytical approach of the impact of through silicon via on the performance of MOS devices

Current innovations in electronics combine performance, size and cost criteria. Nevertheless, in the all-digital era, the 2D technology and the fabrication of CMOS Integrated Circuit are approaching their ultimate limits. As a result, the use of 3D technology in the fabrication of different Integrated Circuits becomes very appealing. Among the aspects of the 3D Integration we find the Through Silicon Vias (TSVs), short vertical interconnects that convey the different layers all kind of signals. 3D integration, first introduced for memory chips, has later found increasing application to other domains in microelectronics. The aim of this research is to investigate the electrical performances of MOS devices which have nearby such a type of interconnects (TSVs) in view of optimizing their behavior with the implementation of an analytical model able to describe the TSVs behavior at the circuit level in order to predict and optimize the performance of MOS devices with 3D-TSV interconnect. The accuracy of this model is eventually validated using numerical TCAD simulations.