Reliability assessment of backward error recovery for SRAM-based FPGAs

Reliability is a major concern for embedded systems. Semiconductor devices used to implement them can suffer from various environmental perturbations. This is more evident when considering SRAM-based FPGA. Perturbations are very frequent and they can limit FPGA´s usability. In this paper, a new fault tolerance approach is presented which try to take advantage of partial dynamic reconfiguration provided by SRAM-based FPGAs. The approach is based on the Backward Error Recovery to mitigate faults on the configuration layer by restoring the correct behavior of the application. Fault injection using emulation is used to evaluate the reliability of the proposed fault mitigation technique and its results are compared to those obtained when configuration scrubbing is used. An improvement of up to 12% for reliability and availability of the Design Under Test is observed.