DocumentCode :
1132913
Title :
On Monte Carlo Testing of Logic Tree Networks
Author :
Agrawal, Pratfiima ; Agrawal, Vishwani D.
Author_Institution :
Department of Electrical Engineering, University of Southern California
Issue :
6
fYear :
1976
fDate :
6/1/1976 12:00:00 AM
Firstpage :
664
Lastpage :
667
Abstract :
It is shown that by a proper selection of the probabilities of 0 and 1 at the inputs, the efficiency of random test generation can be improved. This correspondence includes some results describing the testing of actual logic networks used in a computer.
Keywords :
Combinational tree networks, detection probability, fault detection, logic testing, random test generation.; Circuit faults; Circuit testing; Computer networks; Contracts; Fault detection; Fluctuations; Logic testing; Monte Carlo methods; Probabilistic logic; Radar detection; Combinational tree networks, detection probability, fault detection, logic testing, random test generation.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1976.1674670
Filename :
1674670
Link To Document :
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