Title :
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)
Author :
Lai, Ya-Chun ; Huang, Shi-Yu
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
Abstract :
A BIST-Assisted Timing-Tracking (BATT) scheme is proposed in this paper to facilitate robust read operation in an SRAM design without sacrificing any circuit performance at all. This scheme has very low area overhead since it uses commonly existing memory BIST circuit for tracking the worst-case silicon speed of the bitlines. It is also highly scalable and therefore suitable for an SRAM compiler that needs to support a wide range of different configurations. Measurement results of 8 manufactured chips of a 2 K-bit SRAM design using TSMC 0.18-mum CMOS technology demonstrate that it can indeed rescue one originally failing chip, while still warranting correct functionality of all the other seven chips, even under some injected variations in which conventional schemes may fail badly.
Keywords :
CMOS integrated circuits; SRAM chips; built-in self test; BIST-assisted timing-tracking; SRAM design; TSMC CMOS technology; built-in self-test circuit; memory BIST circuit; size 0.18 mum; storage capacity 2 Kbit; Built-in self-test; CMOS technology; Circuit optimization; Delay; Power amplifiers; Random access memory; Robustness; Silicon; Timing; Voltage; Memory BIST; SRAM; sense amplifier; timing tracking;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.2011042
