Title :
On the Properties of Irredundant Logic Networks
Author_Institution :
Department of Electrical Engineering and the Computer Science Program, University of Southern California
Abstract :
The constraints imposed by various types of irredundancy on the structure of combinational logic networks are investigated. It is shown that the usual notion of irredundancy, here called a-irredundancy, places bounds on the maximum number of inputs to certain types of network structures. A network is called b-redundant if it contains a cascade of single-input gates that can be reduced to either an inverter or a single line. Let Nab(Z) denote all realizations of Z that are both a- and b-irredundant. If N ∈ Nab(Z), then the number of gates in any fan-out-free subnetwork of N is bounded. It is shown that a solution to some important design optimization problems can be found in Nab(Z). It is conjectured that Nāb(Z) is finite and some results supporting this conjecture are presented. For example, it is impossible to construct an arbitrarily long cascade of networks that perform the identity transformation without introducing a- or b-redundancy. A more general type of redundancy, c-redundancy, is defined which includes both a- and b-redundancy as special cases. The class of c-irredundant realizations of Z is finite.
Keywords :
Combinational networks, irredundant networks, logic circuits, logic design optimization, redundancy, redundancy testing, redundancy types.; Circuit faults; Circuit testing; Computer science; Cost function; Design optimization; Inverters; Logic circuits; Logic design; Logic testing; Redundancy; Combinational networks, irredundant networks, logic circuits, logic design optimization, redundancy, redundancy testing, redundancy types.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1976.1674713