DocumentCode
1133494
Title
A Compact High-Speed Parallel Multiplication Scheme
Author
Stenzel, William J. ; Kubitz, William J. ; Garcia, Gilles H.
Author_Institution
Data Systems Division, Hewlett-Packard Company
Issue
10
fYear
1977
Firstpage
948
Lastpage
957
Abstract
This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m X m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 X 24-bit implementation are discussed.
Keywords
Binary multiplication, fast multipliers, generalized counters, partial-product reduction.; Adders; Algorithm design and analysis; Computer science; Counting circuits; Fabrication; Instruments; Large scale integration; NASA; Partitioning algorithms; Read only memory; Binary multiplication, fast multipliers, generalized counters, partial-product reduction.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1977.1674730
Filename
1674730
Link To Document