Title :
An analytical CMOS inverter delay model including channel-length modulations
Author :
Chow, Hwang-Chemg ; Feng, Wu-Shiung
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
9/1/1992 12:00:00 AM
Abstract :
An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations
Keywords :
CMOS integrated circuits; delays; high field effects; integrated logic circuits; logic gates; semiconductor device models; channel-length modulations; high-field effects; inverter delay model; quasi-two-dimensional analysis; saturation region; short-channel MOSFET model; source-drain resistance; Analytical models; Capacitance; Capacitors; Delay effects; Intrusion detection; Inverters; MOS devices; MOSFET circuits; Semiconductor device modeling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
