Title :
Stuck-open testable scan-based CMOS sequential circuits
Author :
Park, Bong-Hee ; Menon, Premachandran R.
Author_Institution :
Dept of Electr. & Comput. Eng., Massachusetts. Univ., Amherst, MA, USA
fDate :
9/1/1992 12:00:00 AM
Abstract :
A testing methodology for applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits is presented. This method requires shifting in only one pattern and requires no special latches in the scan chain. Sufficient conditions for robust testability of all single field-effect transistor (FET) stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. This technique leads to realizations with at most two additional inputs and some additional FET´s in the first-level gates
Keywords :
CMOS integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; field-effect transistor; sequential circuits; stuck-open faults; testable scan-based circuits; testing methodology; two-pattern tests; Circuit faults; Circuit testing; Electrical fault detection; FETs; Fault detection; Latches; Robustness; Semiconductor device modeling; Sequential analysis; Sequential circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
