DocumentCode
1133822
Title
Store Address Generator with On-Line Fault-Detection Capability
Author
Hsiao, M.Y. ; Patel, A.M. ; Pradhan, D.K.
Author_Institution
IBM Corporation
Issue
11
fYear
1977
Firstpage
1144
Lastpage
1147
Abstract
A novel technique for address generation is presented in this correspondence. This scheme has two useful features. Addresses are generated with check bits as an integral part of the address in order to provide multi-fault-detection capability. To date, there exists no such scheme with this feature. Secondly, the addresses generated through this scheme are pseudorandom; therefore, they can be used for storage hierarchies using hash coding techniques.
Keywords
Address generator, binary counter, error-correcting codes, fault-tolerant computing, linear-feedback shift register.; Circuit faults; Circuit testing; Counting circuits; Digital systems; Electrical fault detection; Error correction codes; Fault detection; Random access memory; Read-write memory; Shift registers; Address generator, binary counter, error-correcting codes, fault-tolerant computing, linear-feedback shift register.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1977.1674762
Filename
1674762
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