Efficient multicore implementation of an advanced generator of discrete chaotic sequences

Author

Desnos, Karol ; El Assad, Safwan ; Arlicot, Aurore ; Pelcat, Maxime ; Menard, Daniel

Author_Institution

IETR, INSA Rennes, Rennes, France

fYear

2014

fDate

8-10 Dec. 2014

Firstpage

31

Lastpage

36

Abstract

This paper details the design and implementation performances of an efficient generator of chaotic discrete integer valued sequences. The generator exhibits orbits having very large lengths compared to those given in the literature. It is implemented in C language and parallelized using the Parameterized and Interfaced Synchronous Dataflow Model of Computation (PiSDF MoC). The proposed structure is shown to be scalable, parallel and time efficient. The resulting implementation combines a very long minimal chaotic sequence o_min > 7*2¹²⁸ 32-bit samples and a very high throughput of 173Mbps on 4 cores of a General Purpose Processor.

Keywords

C language; chaos generators; data flow computing; multiprocessing systems; random sequences; C language; PiSDF-MoC; chaotic discrete integer valued sequence generator; general purpose processor; generator design performance; generator implementation performance; multicore implementation; parallelization; parameterized-and-interfaced synchronous dataflow model-of-computation; scalable-parallel-time efficient structure; very-long minimal-chaotic sequence; Bit rate; Chaotic communication; Generators; Multicore processing; Optimization; Parallel processing; Chaotic generator; dataflow model of computation; multicore implementation; performance analysis; pseudo-random number generator;

fLanguage

English

Publisher

ieee

Conference_Titel

Internet Technology and Secured Transactions (ICITST), 2014 9th International Conference for

Conference_Location

London

Type

conf

DOI

10.1109/ICITST.2014.7038770

Filename

7038770