A CMOS Hard-Decision Analog Convolutional Decoder Employing the MFDA for Low-Power Applications

The use of analog circuits to reduce the size and power consumption of channel decoders such as Viterbi decoders has been an active area of research over the recent years. However, the need for digital memory to store the history of the path elimination decisions in a Viterbi decoder, limits the potential advantages that could be offered by an all-analog convolutional decoder implementation. This is especially so in cases where the use of an older silicon process technology is dictated by the application; hence, the power-reduction benefits offered by deep sub-micrometer digital designs cannot be exploited. A novel alternative convolutional decoding method which allows for an entirely analog implementation is the modified feedback decoding algorithm (MFDA). This paper describes the first integrated realization of a convolutional decoder employing the MFDA. The rate-1/2, constraint-length-3 decoder, employs a current-mode analog signal processing core and was fabricated in a 0.6-mum CMOS process technology, occupying an area of 0.5 mm². Measured results show that decoding speeds in excess of 1-Mb/s are possible with virtually no loss in coding gain. Total power consumption is 2.45 mW from a single 3-V supply. Although a hard-decision decoder, conversion to soft-decision decoding requires only the inclusion of a simple analog delay line as shown in the paper. The decoder is dedicated to an implantable biotelemetry system, but it can also find use in other low-power applications. System-level coding simulations are also presented which are useful for the construction of larger decoders where the benefits of the MFDA approach would be more pronounced.