Abstract :
It is shown how any combinational function that can be described by a flow table—or equivalently—is realizable in iterative form—can be realized in tree form. The propagation delay is then proportional to the logarithm of n, the number of inputs, while the logic complexity is a linear function of n. These results are related to various implementations of high-speed binary adders and a proposed new high-speed adder circuit.
Keywords :
Adders, binary adders, carry lookahead, combinational circuits, conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, synthesis, tree circuits.; Adders; Circuit synthesis; Combinational circuits; Delay; Iterative methods; Logic arrays; Logic circuits; Logic testing; Sequential circuits; Signal synthesis; Adders, binary adders, carry lookahead, combinational circuits, conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, synthesis, tree circuits.;
