Memory and Bus Conflict in an Array Processor

The multiassociative processor (MAP) system is a hypothetical machine composed of eight control units (CU´s) and an arbitrary number of processing elements (PE´s). Each CU is allocated a subset of the identical PE´s in order to process a single-instruction-stream-multiple-data-stream program. The eight CU´s must be able to access a common main memory system and transmit data to subsets of the PE´s over a shared data bus system. This paper discusses the analysis of these two components of the system where this analysis relies heavily on three simulation programs. The first program interprets assembly language programs for the hypothetical machine and the other two programs model the memory system and the data bus system. The interpreter is driven by both realistic array processor programs and synthetic programs designed specifically to test the components of the system.