Title :
A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs
Author :
Kim, Kinam ; Lee, Jooyoung
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwaseong, South Korea
Abstract :
Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by trap-assisted gate-induced drain leakage currents depending on trap energy dispersion. Through analyses of full chip retention failure curves and interface trap density ( Dit*) measurements, we propose that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale. As a result, the retention time is eventually to be determined by the main distribution function only.
Keywords :
DRAM chips; leakage currents; nanoelectronics; data retention time; full chip retention failure curve; gate-induced drain leakage current; interface trap density; nanoscaled DRAM; scaled-down cell size; trap energy dispersion; DRAM; Data retention time; gate-induced drain leakage (GIDL) currents; recess channel array transistor (RCAT); trap-assisted tunneling (TAT);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2009.2023248
