DocumentCode :
1135692
Title :
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
Author :
Chen, Song ; Yoshimura, Takeshi
Author_Institution :
Waseda Univ., Kitakyushu
Volume :
27
Issue :
5
fYear :
2008
fDate :
5/1/2008 12:00:00 AM
Firstpage :
858
Lastpage :
871
Abstract :
In this paper, we propose a fixed-outline floorplanning (FOFP) method [insertion-after-remove (IAR) FP]. An elaborated method for perturbing solutions, the IAR, is devised. This perturbation uses a technique of enumerating block positions, which is implemented based on the floorplan-representation sequence pair. The proposed perturbation method can greatly accelerate searching-based algorithms, such as simulated annealing, by skipping many solutions that fail to meet the fixed-outline constraint. Moreover, based on the analysis of the diverse objective functions used in the existing research works, we suggest for the FOFP a new objective function which is still effective when combined with other objectives. Experimental results show that, if area and wirelength are optimized simultaneously, using less time, the proposed method obtains much higher average success rate for the FOFP with various aspect ratios, while the wirelength with the fixed-outline constraint is reduced by 20% on average, compared with the latest fixed-outline floorplanners. On the other hand, we validated once more by experiments that an aspect ratio close to one is beneficial to wirelength, and hence, a larger area weight is necessary for the FOFP with a larger aspect ratio to ensure feasible solutions.
Keywords :
integrated circuit layout; simulated annealing; block-position enumeration; fixed-outline floorplanning; insertion-after-remove floorplanning; objective function; simulated annealing; Acceleration; Constraint optimization; Cost function; Educational products; Educational technology; Perturbation methods; Production systems; Simulated annealing; Transistors; Very large scale integration; Fixed outline; floorplanning; sequence pair (SP);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.917968
Filename :
4492827
Link To Document :
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