Title :
Generation of Optimal Transition Count Tests
Author_Institution :
Department of Electrical Engineering and the Department of Computer Science, University of Southern California
Abstract :
The problem of generating minimum-length transition count (TC) tests is examined for combinational logic circuits whose behavior can be defined by an n-row fault table. Methods are presented for generating TC tests of length n+2 and 2n-1 for fault detection and fault location, respectively. It is shown that these tests are optimal with respect to the class of n-row fault tables in the sense that there exist n-row fault tables that cannot be covered by shorter TC tests. The practical significance of these tests is discussed.
Keywords :
Combinational circuits; fault detection; fault location; fault tables; optimal tests; test generation; transition counting; Circuit faults; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Fault location; Logic circuits; Logic testing; Test equipment; Combinational circuits; fault detection; fault location; fault tables; optimal tests; test generation; transition counting;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1978.1674950