Evaluation of low-energy and high-performance processor using variable stages pipeline technique

A methodology for low-energy and high-performance computing that is essential in mobile and ubiquitous computing is proposed. The dynamic voltage scaling (DVS) is one of the current major methodologies for low-power devices. However by DVS, the lower the chip voltage becomes in the future, the less energy saving is obtained by DVS. Therefore in order to reduce the energy consumption for lower voltage devices, variable stages pipeline (VSP) processor with the latch D-FF selector (LDS)-cell that unifies pipeline stages dynamically and also decreases energy consumption caused by glitch propagations on a low- energy mode is proposed. With its features, the VSP technique can achieve low-energy computing without any dependence on chip voltage. It is shown that the VSP processor can achieve low-energy computing and higher performance computing than the DVS processor in the low-energy mode by evaluating the proposed approach using SpeclNT2000 benchmark suite.