Parasitic modeling and analysis for a 1-Gb/s CMOS laser driver

A differential laser driver (LD) operating at 1 Gb/s has been designed and tested using NSC 0.35-μm CMOS technology. The effect of simultaneous switching noise caused by packaging parasitic was addressed and the parasitic model was developed to predict the exact behavior of circuit performance. With the developed parasitic model, the LD simulation results showed the degradation of the output signal. Thus, the effectiveness of the decoupling capacitor was suggested and investigated through the LD design. However, the test results did not match with the expected results due to the parasitic in the input and output nodes. Hence, the back-annotated analysis was performed with the developed parasitic models and the simulated output of the LD matched with that of the tested results.