High-performance strained Si/SiGe pMOS devices with multiple quantum wells

This paper describes the fabrication and results of the electrical characterization of buried channel Si/SiGe pMOS devices using double and single quantum wells. The devices have been fabricated in an almost standard CMOS technology including shallow trench isolation, rapid thermal annealing, and standard Co/Ti silicidation. The incorporation of 15% and 32% channels provides a strong enhancement (up to 85%) in long-channel mobility. This increased mobility behavior is translated into a 55% higher on-state current for the long-channel devices and a 13% higher on-state current (V_gs-V_T= -1 V and V_ds= -1.5 V) for devices down to L_mask=70 nm while maintaining low leakage and good short-channel and drain induced barrier lowering behavior.