Reconfigurable digital radar receiver implemented in FPGA using Under-sampling, Direct IQ generation, Multi-rate filter and pulse compression

Reconfigurable digital receiver of radar system in FPGA required less computation and FPGA resources. Digital techniques like fast sampling ADC, Direct IQ generation, multi-rate filter, pulse compression are used in this design for improving the performance and reliability of receiver. Digital receiver receives, enhances and converts analog RF return energy into digital signals for further detection processing of target. Xilinx FPGA Virtex 5 is used in this design to give more flexibility in changing receiver parameter like different waveforms, bandwidths, sampling rates etc. Matlab tool develops and simulates the design whereas Xilinx system generator generates the VHDL code. All algorithms in FPGA are implemented in fixed point. In this paper, receiver design can be reconfigured with different bandwidth, sampling rate in FPGA by changing DDC FIR filter and pulse compression coefficients for multichannel receiver application.