Analysis and comparison of cache coherence protocols for a packet-switched multiprocessor

Analytical models are developed for seven existing cache protocols, namely, Write-Once, Write-Through, Synapse, Berkeley, Illinois, Firefly, and Dragon. The protocols are implemented on a multiprocessor with a packet-switched shared bus. The models are based on queuing networks that consist of both open and closed classes of customers. The models incorporate the requests for invalidation signals, write-through, and write-back operations, and the solution is based on the mean value analysis (MVA) algorithm. The performance of these protocols under various system parameters is compared on the basis of the models. It is found that Firefly and Dragon perform better than the others