DocumentCode :
1138525
Title :
Instantaneous Clockless Data Recovery and Demultiplexing
Author :
Analui, Behnam ; Hajimiri, Ali
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Volume :
52
Issue :
8
fYear :
2005
Firstpage :
437
Lastpage :
441
Abstract :
An alternative architecture for instantaneous data recovery for burst-mode communication is introduced. The architecture can perform 1: 
demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of . The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s.
demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of . The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s.Keywords :
Ge-Si alloys; circuit complexity; combinational circuits; delay circuits; demultiplexing; demultiplexing equipment; finite state machines; network synthesis; network topology; synchronisation; 1:2 clockless demultiplexer circuit; 7.5 Gbits/s; SiGe; analog LC transmission line delay cells; burst-mode communication; circuit complexity; combinational circuits; combinational logic circuits; delay circuits; demultiplexing equipment; finite state machines; instantaneous clockless data recovery; network synthesis; network topology; synchronisation; unit interval jitter reduction; Clocks; Delay lines; Demultiplexing; Distributed parameter circuits; Feedback loop; Jitter; Logic; Phase locked loops; Sampling methods; Silicon germanium; Burst-mode communication; combinational logic circuits; delay circuits; delay lines; demultiplexing; emitter coupled logic; finite-state machines (FSMs); passive circuits; transmission lines;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2005.850453
Filename :
1495745
Link To Document :
