High-speed DCFL circuits with very shallow junction GaAs JFETs

Author

Wada, M. ; Okubora, A. ; Takano, C. ; Kawasaki, H. ; Hida, Y. ; Kasahara, J.

Author_Institution

Sony Corp Res. Center, Yokohama, Japan

Volume

36

Issue

7

fYear

1989

fDate

7/1/1989 12:00:00 AM

Firstpage

1387

Lastpage

1388

Abstract

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1×10¹⁸ cm^-3 together with a very shallow junction depth of less than 30 nm for the p⁺-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 μm. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p⁺-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate

Keywords

III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated logic circuits; junction gate field effect transistors; DCFL circuits; GaAs; JFETs; divide-by-four static frequency divider; enhancement-mode J-FETs; gate length; open-tube diffusion; p⁺-gate; power consumption; propagation delay time; ring oscillator; shallow p⁺-layer; transconductance; very shallow junction; Energy consumption; FETs; Flip-flops; Frequency conversion; Gallium arsenide; JFETs; Logic circuits; Thickness control; Transconductance; Zinc;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.30946

Filename

30946