The effect of interconnection resistance on the performance enhancement of liquid-nitrogen-cooled CMOS circuits

The interconnection is modeled as a distributed RLC line driven by an optimal configuration of cascaded inverters. The thin-film resistivity of pure aluminum has been measured to allow accurate prediction of the effect of interconnection resistance on performance. A critical interconnect length is defined as the point at which interconnect resistance begins to dominate propagation delay time. The critical interconnect length is computed at room temperature and liquid-nitrogen temperature for present-day and scaled CMOS technologies and compared to the maximum interconnect length expected in state-of-the-art VLSI circuits