A parameterized cell design for high-Q, variable width and spacing spiral inductors

The on-chip planar spiral inductors having variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q). In this paper, we present an efficient parameterized cell (pcell) design in cadence using SKILL scripts for automatic layout generation of these complex, high-Q, variable W&S spiral inductors comprising of single ended and symmetric structures with rectangular, hexagonal, octagonal and circular spirals. Electromagnetic simulations are performed on the inductor layouts generated using the developed pcells. The constant W&S and variable W&S spiral inductor structures are fabricated in a 0.18 μm silicon on insulator process. Measurements show ~25% improvement in the quality factor of variable W%S spiral inductors compared to their constant W&S counterparts and also validates the proper operation of the developed inductor parameterized cells. The presented variable W&S inductor pcell significantly reduces the layout design time of RF circuit designers and also helps in the design automation of these complex inductor structures to boost their own performance and the RF circuits as well.