DocumentCode :
1139537
Title :
A new 2-D systolic digital filter architecture without global broadcast
Author :
Van, Lan-Da
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
10
Issue :
4
fYear :
2002
Firstpage :
477
Lastpage :
486
Abstract :
In this paper, we propose two-dimensional (2-D) systolic-array infinite-impulse response (IIR) and finite-impulse response (FIR) digital filter architectures without global broadcast, by the hybrid of a modified reordering scheme and a new systolic transformation. This architecture has local broadcast, lower-quantization error, and zero latency without sacrificing the number of multipliers, as well as delay elements under the satisfactory critical period. Furthermore, we extend this new architecture to a useful 2-D systolic cascade-form architecture and provide the comprehensive error analysis for the proposed architectures.
Keywords :
FIR filters; IIR filters; VLSI; cascade networks; digital integrated circuits; error analysis; systolic arrays; two-dimensional digital filters; 2D systolic cascade-form architecture; 2D systolic digital filter architecture; FIR digital filter; IIR digital filter; delay elements; error analysis; finite-impulse response filter; global broadcast free architecture; infinite-impulse response filter; local broadcast; modified reordering scheme; multipliers; quantization error reduction; systolic array; systolic transformation; zero latency; Application specific integrated circuits; Delay; Digital filters; Digital signal processing; Error analysis; Finite impulse response filter; IIR filters; Quantization; Signal processing; Two dimensional displays;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2002.800531
Filename :
1177350
Link To Document :
بازگشت