Title :
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
Author_Institution :
IBM Thomas J. Watson Research Center
fDate :
3/1/1979 12:00:00 AM
Abstract :
An efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM´s) for any decoder implementation is presented. Another algorithm which does not assume any particular wired logic behavior of simultaneously accessed storage locations, is also presented.
Keywords :
Arbitrary decoder implementation; fault detection; multiple stuck-at faults; optimal algorithm; random access memories; wired logic behavior; Algorithm design and analysis; Circuit faults; Circuit testing; Combinational circuits; Decoding; Electrical fault detection; Fault detection; Logic testing; Random access memory; Registers; Arbitrary decoder implementation; fault detection; multiple stuck-at faults; optimal algorithm; random access memories; wired logic behavior;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1979.1675331
